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Integrated Circuit Systems, Inc.
ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Four LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following applications: SONET/SDH, SATA, or 10Gb Ethernet * Output frequency range: 140MHz - 170MHz, 560MHz - 680MHz * VCO range: 560MHz - 680MHz * Crystal oscillator and CLK range: 17.5MHz - 21.25MHz * RMS phase jitter @ 622.08MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.82ps (typical) * RMS phase jitter @ 156.25MHz output, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) * RMS phase jitter @ 155.52MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.94ps (typical) * Full 3.3V supply mode * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS843004I-04 is a 4 output LVPECL Synthesizer optimized to generate clock HiPerClockSTM frequencies for a variety of high performance applications and is a member of the HiPerClocks TM family of high perfor mance clock solutions from ICS. This device can select its input reference clock from either a crystal input or a singleended clock signal. It can be configured to generate 4 outputs with individually selectable divide-by-one or divide-by-four function via the 4 frequency select pins ( F _ S E L [ 3 : 0 ] ) . T h e I C S 8 4 3 0 0 4 I - 0 4 u s e s I C S ' 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical r ms phase jitter. This ensures that it will easily meet clocking requirements for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/ OC12/OC-48). This device is suitable for multi-rate and multiple port line card applications. The ICS843004I-04 is conveniently packaged in a small 24-pin TSSOP package.
IC S
BLOCK DIAGRAM
XTAL_IN
PIN ASSIGNMENT
/1 Phase Detector VCO /4 0 1
OSC
XTAL_OUT CLK Pulldown INPUT_SEL Pulldown
0
Q0 nQ0
1
M = /32
MR F_SEL0
Pulldown Pullup
0 1
Q1 nQ1
nQ1 Q1 VCCo Q0 nQ0 MR F_SEL3 nc VCCA F_SEL0 VCC F_SEL1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
nQ2 Q2 VCCO Q3 nQ3 VEE F_SEL2 INPUT_SEL CLK VEE XTAL_IN XTAL_OUT
F_SEL1 Pullup
0 1
ICS843004I-04
Q2 nQ2
F_SEL2
Pullup
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
0 1
Q3 nQ3
F_SEL3 Pullup
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Integrated Circuit Systems, Inc.
ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Type Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3. No connect. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pins. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or CLK inputs as the the PLL Reference source. Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 7, 10, 12, 18 8 9 11 13, 14 15, 19 16 17 20, 21 23, 24 Name nQ1, Q1 VCCO Q0, nQ0 MR F_SEL3, F_SEL0, F_SEL1, F_SEL2 nc VCCA VCC XTAL_OUT, XTAL_IN VEE CLK INPUT_SEL nQ3, Q3 Q2, nQ2 Output Power Ouput Input
Input Unused Power Power Input Power Input Input Output Output
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. OUTPUT CONFIGURATION
Inputs F_SELx 0 1 0 1 0 1 0 1 XTAL (MHz) 19.44 19.44 18.75 18.75 19.53125 19.53125 20.141601 20.141601
AND
FREQUENCY RANGE FUNCTION TABLE
Divider Value /1 /4 /1 /4 /1 /4 /1 /4 Output Frequency (MHz) Q0/nQ0:Q3/nQ3 622.08 155.52 60 0 150 625 156.25 644.5312 161.13 Application SONET/SDH SATA 10 Gigabit Ethernet 10 Gigabit Ethernet 66B/64B FEC
VCO (MHz) 622.08 622.08 600 600 625 625 644.5312 644.5312
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ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, JA 70C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 120 10 120 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current CLK, MR, INPUT_SEL F_SEL0:F_SEL3 IIL Input Low Current CLK, MR, INPUT_SEL F_SEL0:F_SEL3 VCC = VIN = 3.465 VCC = VIN = 3.465 VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum Typical 2 -0.3 Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 17.5 Typical Maximum 21.25 50 7 1 Units MHz pF mW
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Fundamental
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT tsk(o) Parameter Output Frequency Output Skew; NOTE 1, 2, 3 155.52MHz, Integration Range: 12kHz - 20MHz 156.25MHz, Integration Range: 1.875MHz - 20MHz 622.08MHz, Integration Range: 12kHz - 20MHz 20% to 80% 0.94 0.57 82 175 675 52 60 Test Conditions Output Divider = /1 Output Divider = /4 Minimum 560 140 Typical Maximum 680 170 75 Units MHz MH z ps ps ps ps ps % %
tjit(O)
RMS Phase Jitter (Random); NOTE 4
t R / tF odc
Output Rise/Fall Time Output Duty Cycle
Output Divider = /4 48 Output Divider = /1 40 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Output skew measurements taken with all outputs in the same divide configuration. NOTE 4: Please refer to the Phase Noise Plot.
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V VCCA = 2V nQx Qx VCC, VCCO
Qx
SCOPE
nQy Qy
tsk(o)
LVPECL
VEE
nQx
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
OUTPUT SKEW
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004I-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843004I-04 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R2, C3 and C4 should also be located as close to the VCCA pin as possible.
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example for ICS843004I-04. In this example, the input is a 19.44MHz parallel resonant crystal with load capacitor CL=18pF. The 22pF frequency fine tuning capacitors are used C1 and C2. This example also shows general logic control input handling. For decoupling capacitors, it is
MR F_SEL3 VCC VCCA R2 10 3.3V C3 10uF C4 0.01u R3 133 VCCO Zo = 50 Ohm + VCC F_SEL0 R5 133
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
F_SEL1 12 11 10 9 8 7 6 5 4 3 2 1
Zo = 50 Ohm
-
F_SEL1 VCC F_SEL0 VCCA NC F_SEL3 MR nQ0 Q0 VCCO Q1 nQ1
U1 843004i-04
R4 82.5
R6 82.5
RD1 Not Install
RD2 1K
XTAL_OUT XTAL_IN VEE CLK INPUT_SEL F_SEL2 VEE nQ3 Q3 VCCO Q2 nQ2
To Logic Input pins
To Logic Input pins
VCC=3.3V VCCO=3.3V
(U1-3)
VCC
(U1-11)
(U1-22)
13 14 15 16 17 18 19 20 21 22 23 24
Zo = 50 Ohm C1 0.1uF C2 0.1uF C3 0.1uF Zo = 50 Ohm C2 22pF VCC Q1 Ro ~ 7 Ohm R8 43 Driv er_LVCMOS INPUT_SEL F_SEL2 Zo = 50 Ohm X1 19.44MHz 18pF C1 22pF VCCO R5 50 R6 50 +
Optional Y-Termination
R7 50
FIGURE 5. ICS844004I-04 SCHEMATIC EXAMPLE
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004I-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843004I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 415.8 + 120mW = 535.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming an air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.536W * 65C/W = 119.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 24-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
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3. Calculations and Equations.
ICS843004I-04
FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a
termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V
CC_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V
OL_MAX
CC_MAX
(VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843004I-04 is: 2273
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKSTM CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Marking Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843004AGI-04 ICS843004AGI-04T ICS843004AGI-04LF ICS843004AGI-04LFT ICS843004AI04 ICS843004AI04 ICS43004AI04L ICS43004AI04L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AGI-04
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